Alchip Reveals 3DIC Design Optimization Keys

Two Industry Leaders Undertook Daunting Advanced Technology Challenges The paper, “Efficient 3D Chiplet Stacking Using TSMC-SoIC®,” describes how Alchip used a third-party EDA tool to overcome four complex technical challenges. In the paper, Erez Shaizaf, Alchip's Chief Technical Officer, identifies three major barriers to 3DIC success: power delivery, dies electrical interconnect, and system-wide thermal challenges. He points out that power delivery really encompasses three separate...

San Jose, 17/10/2024 (informazione.it - comunicati stampa - economia)

The paper, “Efficient 3D Chiplet Stacking Using TSMC-SoIC®,” describes how Alchip used a third-party EDA tool to overcome four complex technical challenges.

In the paper, Erez Shaizaf, Alchip's Chief Technical Officer, identifies three major barriers to 3DIC success: power delivery, dies electrical interconnect, and system-wide thermal challenges.

He points out that power delivery really encompasses three separate challenges: power integrity, power grid design (including through silicon via distribution), and power integrity simulation and sign-off.

Dies electrical interconnect are identified as low clock skew across dies, process variation immunity, noise immunity, data transmission across different power domains, inter-die setup/hold timing margin, PPA optimized IO cells for clock and data, and redundancy strategy.

The paper details thermal challenges as 3DIC thermal characterization covering increased power density, 3D non-uniform power mapping, 3D thermal crosstalk effects, package, and system cooling solution modeling.

“Without a doubt, TSMC's 3D silicon stacking System-on-Integrated-Chips (SoIC) enables the next level of performance for data center chips, however, it poses new design challenges and considerations. Alchip has been collaborating for many years with its key EDA partner to accelerate multi-die designs. This paper clearly presents solutions for optimizing designs on TSMC-SoIC® technology, using third-party EDA tools and Alchip methodologies,” Shaizaf explained.

Alchip stated that it will also discuss the paper's findings at other global TSMC OIP events in Japan, China, Taiwan, and Europe, from October to November 2024.

About Alchip

Alchip Technologies Ltd., established in 2003 and headquartered in Taipei, Taiwan, is a global leader in silicon design and production services for companies developing complex, high-volume ASICs and SoCs. Renowned for accelerating time-to-market and offering cost-effective solutions, Alchip excels in high-performance ASICs with expertise in advanced packaging (CoWoS-S/R), 2.5D/3DIC, and Chiplet design. Serving industry giants in AI/HPC, supercomputing, networking, and consumer electronics, Alchip has cemented its reputation for cutting-edge innovation. The company is publicly listed on the Taiwan Stock Exchange (TWSE: 3661).

For more information, please visit our website:  http://www.alchip.com